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W631GG6KB
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
Command *3
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WL = AL + CWL
Address *4
Bank
Col n
t DQSS (min)
t WPRE(min)
t DQSS t DSH
t DSH
t DSH
t DSH
t WPST(min)
DQS, DQS#
t DQSH(min)
t DQSL
t DQSH
t DQSL
t DQSH
t DQSL
t DQSH
t DQSL
t DQSH
t DQSL(min)
t DSS
t DSS
t DSS
t DSS
t DSS
DQ *2
Din
n
Din
n+2
Din
n+3
Din
n+4
Din
n+6
Din
n+7
DM
t DQSS (nominal)
t WPRE(min)
t DSH
t DSH
t DSH
t DSH
t WPST(min)
DQS, DQS#
t DQSH(min)
t DQSL
t DQSH
t DQSL
t DQSH
t DQSL
t DQSH
t DQSL
t DQSH
t DQSL(min)
t DSS
t DSS
t DSS
t DSS
t DSS
DQ *2
Din
n
Din
n+2
Din
n+3
Din
n+4
Din
n+6
Din
n+7
DM
t DQSS
t DQSS (max)
t WPRE(min)
t DSH
t DSH
t DSH
t DSH
t WPST(min)
DQS, DQS#
t DQSH(min)
t DQSL
t DQSH
t DQSL
t DQSH
t DQSL
t DQSH
t DQSL
t DQSH
t DQSL(min)
t DSS
t DSS
t DSS
t DSS
t DSS
DQ
Din
n
Din
n+2
Din
n+3
Din
n+4
Din
n+6
Din
n+7
DM
TRANSITIONING DATA
DON'T CARE
Notes:
1. BL8, WL = 5 (AL = 0, CWL = 5)
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. t DQSS must be met at each rising clock edge.
Figure 40 – Write Timing Definition and Parameters
8.14.3 Write Data Mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR3 SDRAMs,
consistent with the implementation on DDR2 SDRAMs. It has identical timings on write operations as
the data bits as shown in Figure 40, and though used in a unidirectional manner, is internally loaded
identically to data bits to ensure matched system timing. DM is not used during read cycles.
Publication Release Date: Dec. 09, 2013
Revision A05
- 57 -
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